1. Field of the Invention
The present invention generally relates to a semiconductor memory device, and more particularly relates to a nonvolatile memory device in which data can be electrically written and erased.
2. Description of the Related Art
Recently, a flash EEPROM (Electrically Erasable and Programmable ROM) has been developed mainly as a semiconductor memory device in which data can be electrically written and erased. The flash EEPROM is referred to as a flash memory hereinafter. FIG. 1 is a block diagram showing a flash memory. In the flash memory shown in FIG. 1, a memory-cell array is divided into a plurality of erasable units, each of the erasable units being called a block. Blocks 0 through 10 are placed in the memory-cell array forming a matrix structure of the blocks. Additionally, one of the blocks placed in the matrix structure is divided into a plurality of units called boot blocks. Boot blocks 0 through 7 are arranged so that the boot blocks 0 through 7 can correspond to the blocks placed in the memory-cell array.
The matrix structure of the blocks includes an empty space where no block is placed therein. A memory area called a hidden block 12 provided outside a main memory area is placed in the empty space. The hidden block 12 stores, for instance, product information about the flash memory shown in FIG. 1. Since the hidden block 12 is placed outside the main memory area, the flash memory does not have an address used for selecting the hidden block 12. Thus, in a case of selecting the hidden block 12, the following steps are performed by the flash memory. A hidden-mode command is initially inputted to a command register 14 of the flash memory, thereby shifting an operation mode of the flash memory to a hidden mode. In the hidden mode, all the accesses to the main memory area are prohibited. Subsequently, the hidden block 12 is selected by temporarily using an address regularly used for selecting a block in the main memory area. It should be noted that a column selecting method is shared between the hidden block 12 and other blocks in the main memory area for preventing increase in a chip size of the flash memory. For instance, in the hidden mode, a block-selecting decoder 16 unselects the blocks 0 through 10 and the boot blocks 0 through 7 even if a block address is inputted to the block-selecting decoder 16. In addition, the block-selecting decoder 16 deactivates X-decoders of the blocks 0 through 10 and of the boot blocks 0 through 7. Furthermore, the block-selecting decoder 16 activates only an X-decoder of the hidden block 12 and the vertical block V0 including the hidden block 12, thereby selecting the hidden block 12.
FIG. 2 is a block diagram showing another flash memory. A segmental word line method is adapted to a word line decoding method in the flash memory shown in FIG. 2. In the segmental word line method, a horizontal direction (a horizontal block) and a vertical direction (a vertical block) are selected respectively by a global X-decoder and a local X-decoder in the flash memory. When an operation mode of the flash memory shown in FIG. 2 is shifted to the hidden mode, both the horizontal and vertical directions become not selectable. Additionally, only a local X-decoder of the hidden block 12 is activated. A column corresponding to the hidden block 12 is selected by activating only the vertical block V0 including the hidden block 12 similarly to the above-described flash memory shown in FIG. 1.
With recent low-voltage technology advancement, data cannot be read from a memory cell provided in a block at a gate level equal to a voltage level of a power source. Consequently, with such advancement, a flash memory including a technology to boost a word line voltage above the voltage level of the power source is recently found in an increasing number. The boosted voltage is supplied to a power source of an X-decoder of a block selected by boosted-voltage supply circuits P0 through P10, and SP0 through SP7, each of the boosted-voltage supply circuits being provided to its corresponding block. The hidden block 12 similarly includes a boosted-voltage supply circuit HP. When the operation mode of the flash memory is shifted to the hidden mode, only the boosted-voltage supply circuit HP of the hidden block 12 is activated, and supplies the boosted voltage to a power source of an X-decoder corresponding to the hidden block 12. A value of the boosted voltage is determined by a ratio of a capacitance of a capacitor used for boosting a voltage to a load capacitance measured from a voltage-boosting circuit 22 to a word line. If the load capacitance decreases, the value of the boosted voltage increases. Since a size of the hidden block 12 is often much smaller than the size of a block in the main memory area, the value of the boosted voltage at the power source of the X-decoder corresponding to the hidden block 12 is higher than the boosted voltage at the block when both the hidden block 12 and the block in the main memory area use the same capacitor for boosting voltage.
Recently, there has been a market demand for a flash memory that can store a command used for shifting from a hidden mode to a regular mode therein. In other words, a structure of such a flash memory should be designed so that a block in a main memory area can be selected in the hidden mode. However, as describe above, the hidden block does not have its own address, and thus a method of selecting the hidden block is necessary. Accordingly, a method as describe below has been suggested. Since all the blocks in the main memory area are not necessarily used in the hidden mode, one of the blocks and boot blocks provided in the main memory area is swapped logically with the hidden block, and thus the hidden block can be selected by use of an address of one of the blocks and the boot blocks provided in the main memory area. In other words, the hidden block is selected if the address of one of the blocks and the boot blocks that has been swapped with the hidden block is inputted in the hidden mode. Additionally, if a block address other than the address of the swapped block or boot block is inputted, a block or a boot block corresponding to the block address is selected. By setting any block or any boot block logically swapped with the hidden block, the hidden block can obtain its memory address. However, a circuit structure of the flash memory must be designed so that only the hidden block can be selected, but not the block or the boot block logically swapped with the hidden block, thereby causing increase in the size of a flash memory chip and in a period for developing such a flash memory chip.
In addition, a flash memory whose supply voltage is 3 V has become mainstream in production of flash memories recently. Thus, such flash memory must include a voltage-boosting circuit for boosting voltage at a word line corresponding to each block therein. A value of the boosted voltage depends on the load capacitance as describe above. Since a memory area of the hidden block is much smaller than that of blocks in the main memory area, a value of the boosted voltage supplied to the hidden block is much higher than the boosted voltage supplied to the blocks in the main memory area. As the value of the boosted voltage supplied to the hidden block becomes high, a possibility of data stored in memory cells of the hidden block being damaged such by a charge gain increases. Accordingly, reliability of data stored in the hidden block is lost. On the other hand, by decreasing the value of the boosted voltage supplied to the hidden block to a voltage level at which the reliability of the data stored in the hidden block is not lost, data cannot be read from a block located in the main memory area when the block is selected, since the boosted voltage becomes too low.
One of methods to solve the above-described problem is to provide a capacitor for boosting a voltage for each of the hidden block and the blocks in the main memory area, and to switch capacitors depending on an operation mode of the flash memory. By applying such a method to the flash memory, the boosted voltages for the hidden block and the blocks in the main memory area are stabilized. However, a time to set a capacitance of each capacitor is long. Additionally, an area size of a flash memory chip increases by providing separate capacitors to the flash memory. Furthermore, in a case of applying the segmental word line method to the flash memory, the boosted voltage is supplied to a global word line in addition to word lines, thereby affecting the value of the boosted voltage at word lines for the hidden block and the blocks in the flash memory.
Accordingly, it is a general object of the present invention to provide a semiconductor memory device enabling selection of an address of a memory area located outside a main memory area. A more particular object of the present invention is to provide a semiconductor memory device enabling efficient selection of an address of a memory area located outside a main memory area with a simple circuit structure, thereby shortening a period for developing the circuit structure of the semiconductor memory device and increasing reliability of operations at a low voltage.
The above-described object of the present invention is achieved by a semiconductor memory device including a primary memory area including a plurality of memory blocks arranged in rows and columns, the plurality of memory blocks including a predetermined memory block; a secondary memory area including a hidden memory block situated in the same column as the predetermined memory block; a decision circuit selecting one of a first mode for reading first data from the primary memory area and a second mode for reading second data from the secondary memory area, the decision circuit outputting a signal when the second mode and an address of the predetermined memory block are specified; a column decoder selecting a column corresponding to a column address inputted thereto; and a word-line decoder selecting a word line of the hidden memory block by boosting a word line of an adjacent memory block included in the primary memory area in response to the signal, the word-line decoder being included in the adjacent memory block, wherein the second data is read from the hidden memory block when the column decoder and the word-line decoder select the column corresponding to the hidden memory block and the word line of the hidden memory block respectively.
According to the present invention, the column corresponding to the hidden memory block can be selected just by inputting the address of the predetermined memory block because the hidden memory block and the predetermined memory block are logically swapped. Therefore, neither a change in a circuit structure nor an additional control circuit is necessary for selecting the column in the semiconductor memory device because of using the address of the predetermined memory block. Additionally, a memory block included in the primary memory area can be easily selected in the second mode with few modifications of the circuit structure in the semiconductor memory device.
Additionally, a load capacitance generated for reading data from the hidden memory block and a load capacitance generated for reading data from a memory block included in the primary memory area become substantially equal by sharing a word-line decoder of the adjacent memory block included in the primary memory area with the hidden memory block. Accordingly, a value of a boosted voltage used for reading data from the hidden memory block and a value of a boosted voltage used for reading data from a memory block included in the primary memory area can be equalized.
As described above, selection of a memory address of the secondary memory area is efficiently executed in the semiconductor memory device. Additionally, a period for designing such an efficient circuit structure of the semiconductor memory device is shortened. Furthermore, reliability of operations at a low voltage in the semiconductor memory device is increased.
Other objects, features and advantages of the present invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.